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Espressif Systems /ESP32-P4 /SDHOST /DLL_CLK_CONF

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Interpret as DLL_CLK_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DLL_CCLK_IN_SLF_EN)DLL_CCLK_IN_SLF_EN 0 (DLL_CCLK_IN_DRV_EN)DLL_CCLK_IN_DRV_EN 0 (DLL_CCLK_IN_SAM_EN)DLL_CCLK_IN_SAM_EN 0DLL_CCLK_IN_SLF_PHASE 0DLL_CCLK_IN_DRV_PHASE 0DLL_CCLK_IN_SAM_PHASE

Description

SDIO DLL clock control register.

Fields

DLL_CCLK_IN_SLF_EN

Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1.
DLL_CCLK_IN_DRV_EN

Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1.
DLL_CCLK_IN_SAM_EN

Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1.
DLL_CCLK_IN_SLF_PHASE

It’s used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1.
DLL_CCLK_IN_DRV_PHASE

It’s used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1.
DLL_CCLK_IN_SAM_PHASE

It’s used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data